Electrical interconnections are utilized for numerous semiconductor devices and assemblies. The interconnections can be utilized in, for example, electrically connecting source/drain regions of either p-type metal-oxide-semiconductor (PMOS) field effect transistors or n-type metal-oxide-semiconductor (NMOS) field effect transistors. The electrical connections can also be utilized for coupling PMOS transistor devices with NMOS transistor devices in complementary metal-oxide-semiconductor (CMOS) structures. Exemplary devices which can utilize CMOS structures are CMOS inverters and various static random access memory (SRAM) constructions.
Continuing goals of semiconductor device processing are to increase the scale of integration, simplify processing, and reduce costs. It is desired to create new methods of forming electrical interconnections which progress toward one or more of such continuing goals.
Inventive aspects described herein can be particular useful for forming electrical interconnections to source/drain regions associated with field effect transistors. However, it is to be understood that although the invention is primarily described herein relative to such application, the invention can also be utilized in other semiconductor fabrication applications, as will be recognized by persons of ordinary skill in the art.